Dynamic random access memory (DRAM) semiconductor devices and static random access memory (SRAM) semiconductor devices typically include an insulating layer of a dielectric material to electrically separate one conductive layer from another. Often, the two conductive layers are connected by means of a hole, commonly known as a "contact" or "via," in the insulating layer. Sometimes the via must have a sloped or faceted profile to provide proper step coverage of appropriate thickness of the conductive layer. Vertical contact profiles often result in unacceptable step coverage and excessively sloped profiles provide good step coverage but result in highly enlarged vias. Enlarged vias may cause electrical shorting between or within conductive layers and may also reduce the density of the circuit features by limiting the proximity of the devices. Thus, providing an adequate contact slope is critical to achieving acceptable contact step coverage.
U.S. Pat. No. 5,320,981 to Blalock describes a process for forming a sloped via. In this process, a photoresist mask is used to define an etch area on a dielectric layer. The dielectric layer is etched either isotropically or anisotropically to expose an underlying conductive layer. After the dielectric layer has been etched, the photoresist mask is removed and a second etch is performed. This second etch is a plasma etch and is conducted with a material, such as argon, krypton or xenon, so that as close as possible to a purely physical, as opposed to chemical, erosion takes place. The second etch forms a facet in the side walls of the via and redeposits the eroded dielectric material onto the opposite side wall.
However, when a photoresist material is used during etching of a via, particles of the photoresist material become deposited in the resulting via and on the conductive material. These particles of photoresist material affect the subsequent step coverage and the resulting conductivity of the semiconductor device. Further, plasma etching of a material is not a selective process and in the case of facet etching, portions of the semiconductor device other than the portion being facet etched may be damaged. Thus, a need still exists in the art for a process for forming a semiconductor devices having a gradual slope contact.